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Vito Castellana

High Performance Computing
Post Masters RA
Pacific Northwest National Laboratory
PO Box 999
MSIN: J4-30
Richland, WA 99352

PNNL Publications


  • Castellana VG, A Tumeo, and F Ferrandi. 2014. "An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems." In Design, Automation and Test in Europe Conference and Exhibition (DATE), March 24-28, 2014, Dresden, Germany, pp. 1-4.  Institute of Electrical and Electronics Engineers, Piscataway, NJ. 


  • Morari A, VG Castellana, DJ Haglin, JT Feo, JR Weaver, A Tumeo, and O Villa. 2013. "Accelerating semantic graph databases on commodity clusters." In IEEE International Conference on Big Data (Big Data 2013), October 6-9, 2013, Silicon Valley, California, pp. 768-772.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/BigData.2013.6691650
  • Castellana VG, A Tumeo, O Villa, DJ Haglin, and J Feo. 2013. "Composing Data Parallel Code for a SPARQL Graph Engine." In IEEE International Conference on Social Computing (SocialCom 2013), September 8-14, 2013, Alexandria, Virginia, pp. 691-699.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/SocialCom.2013.104

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