Senior Computer Scientist
Senior Computer Scientist

Biography

Dr. Vito Giovanni Castellana received an MSc (cum laude) in computer engineering in 2010 and a PhD in computer science and engineering in 2014 from the Polytechnic University of Milan, Italy. He is a senior computer scientist with Pacific Northwest National Laboratory’s High-Performance Computing group, which he joined in 2012. His research interests include design automation and high-level synthesis, parallel programming, big data and graph analytics, and compiler technologies. He is the architect and principal developer of the Scalable High-performance Algorithms (SHAD) and Data-structures C++ Library.

Research Interest

  • C++
  • C/C++ Standard Template Library
  • Compilers
  • Computer Architecture
  • Graph Analytics
  • Graph Databases
  • Hardware Description Language
  • High-Performance Computing
  • Software Development
  • Software Engineering

Education

  • PhD in information engineering, Polytechnic University of Milan (2014)
  • MSc in computer engineering, Polytechnic University of Milan (2010)
  • BS in computer science, Polytechnic Institute of Bari (2008)

Publications

2022

  • Bohm Agostini N., S. Curzel, A.M. Limaye, V.C. Amatya, M. Minutoli, V.G. Castellana, and J.B. Manzano Franco, et al. 2022. "The SODA Approach: Leveraging High-Level Synthesis for Hardware/Software Co-design and Hardware Specialization: Invited." In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC 2022), July 10-14, 2022, San Francisco, CA, 1359-1362. New York, New York:Association for Computing Machinery. PNNL-SA-172445. doi:10.1145/3489517.3530628
  • Bohm Agostini N., S. Curzel, J. Zhang, A.M. Limaye, C. Tan, V.C. Amatya, and M. Minutoli, et al. 2022. "Bridging Python to Silicon: The SODA Toolchain." IEEE Micro 42, no. 5:78 - 88. PNNL-SA-169276. doi:10.1109/MM.2022.3178580
  • Curzel S., N. Bohm Agostini, V.G. Castellana, M. Minutoli, A.M. Limaye, J.B. Manzano Franco, and J. Zhang, et al. 2022. "End-to-end Synthesis of Dynamically Controlled Machine Learning Accelerators." IEEE Transactions on Computers 71, no. 12:3074 - 3087. PNNL-SA-169650. doi:10.1109/TC.2022.3211430
  • Minutoli M., V.G. Castellana, N. Saporetti, S. Devecchi, M. Lattuada, P. Fezzardi, and A. Tumeo, et al. 2022. "Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics." IEEE Transactions on Computers 71, no. 3:520-533. PNNL-SA-144167. doi:10.1109/TC.2021.3057860
  • Wu N., V.G. Castellana, and H. Kaiser. 2022. "Towards Superior Software Portability with SHAD and HPX C++ Libraries." In Proceedings of the 19th ACM International Conference on Computing Frontiers (CF 2022), May 17-19, 2022, Turin, Italy, 251-257. New York, New York:Association for Computing Machinery. PNNL-SA-171823. doi:10.1145/3528416.3530784

2021

  • Castellana V.G., A. Tumeo, and F. Ferrandi. 2021. "High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers." In IEEE International Parallel & Distributed Processing Symposium (IPDPS 2021), May 17-21, 2021, Virtual, Online, Paper No. 9460500. Piscataway, New Jersey:IEEE. PNNL-SA-157406. doi:10.1109/IPDPS49936.2021.00028
  • Castellana V.G., and M. Minutoli. 2021. "Productive Programming of Distributed Systems with the SHAD C++ Library." In Proceedings of the 30th International Symposium on High-Performance Parallel and Distributed Computing (HPDC '21), June 21-25, 2021, Virtual, Online, 263 -264. New York, New York:Association for Computing Machinery. PNNL-SA-162110. doi:10.1145/3431379.3462765
  • Curzel S., N. Bohm Agostini, S. Song, I. Dagli, A.M. Limaye, C. Tan, and M. Minutoli, et al. 2021. "Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators." In IEEE/ACM International Conference On Computer Aided Design (ICCAD 2021), November 1-4, 2021, Munich, Germany, 1-7. Piscataway, New Jersey:IEEE. PNNL-SA-166239. doi:10.1109/ICCAD51958.2021.9643474
  • Ferrandi F., V.G. Castellana, S. Curzel, P. Fezzardi, M. Fiorito, M. Lattuada, and M. Minutoli, et al. 2021. "Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications." In 58th ACM/IEEE Design Automation Conference (DAC 2021), December 5-9, 2021, San Francisco, CA, 1327-1330. Piscataway, New Jersey:IEEE. PNNL-SA-160619. doi:10.1109/DAC18074.2021.9586110
  • Zhang J., N. Bohm Agostini, S. Song, C. Tan, A.M. Limaye, V.C. Amatya, and J.B. Manzano Franco, et al. 2021. "Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis." In IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021), July 7-9, 2021, Virtual, 218-225. Piscataway, New Jersey:IEEE. PNNL-SA-163507. doi:10.1109/ASAP52443.2021.00040

2020

  • Minutoli M., V.G. Castellana, C. Tan, J.B. Manzano Franco, V.C. Amatya, A. Tumeo, and D. Brooks, et al. 2020. "SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators." In Proceedings of the 39th International Conference On Computer-Aided Design (ICCAD 2020), November 2-5, 2020, Virtual Conference, edited by Y. Xie, Article No. 98. New York, New York:Association for Computing Machinery. PNNL-SA-155356. doi:10.1145/3400302.3415781
  • Tumeo A., M. Minutoli, V.G. Castellana, J.B. Manzano Franco, V.C. Amatya, D. Brooks, and G. Wei. 2020. "Invited: Software defined accelerators from learning tools environment." In Invited: Software defined accelerators from learning tools environment, 1-6. Piscataway, New Jersey:IEEE. PNNL-SA-152847. doi:10.1109/DAC18072.2020.9218489

2019

  • Castellana V.G., M. Drocco, J.T. Feo, J. Firoz, T.A. Kanewala, A. Lumsdaine, and J.B. Manzano Franco, et al. 2019. "A Parallel Graph Environment for Real-World Data Analytics Workflows." In Design, Automation & Test in Europe Conference & Exhibition (DATE 2019), March 25-29, 2019, Florence, Italy, 1313-1318. Piscataway, New Jersey:IEEE. PNNL-SA-140268. doi:10.23919/DATE.2019.8715196
  • Castellana V.G., M. Minutoli, A. Tumeo, M. Lattuada, P. Fezzardi, and F. Ferrandi. 2019. "Software Defined Architectures for Data Analytics." In Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASPDAC 2019), January 21-24, 2019, Tokyo, Japan, 711-718. New York, New York:ACM. PNNL-SA-139669. doi:10.1145/3287624.3288754

2018

  • Castellana V.G., and M. Minutoli. 2018. "SHAD: the Scalable High-performance Algorithms and Data-structures Library." In 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), May 1-4, 2018, Washington, DC, 442-451. Los Alamitos, California:IEEE Computer Society. PNNL-SA-132254. doi:10.1109/CCGRID.2018.00071
  • Tumeo A., V.G. Castellana, and J.T. Feo. 2018. "Foreword: 8th Workshop on Irregular Applications: Architectures and Algorithms." In IEEE/ACM 8th Workshop on Irregular Applications: Architectures and Algorithms (IA3 2018), November 12, 2018, Dallas, TX, 1, vii-viii. Los Alamitos, California:IEEE Computer Society. PNNL-SA-143418. doi:10.1109/IA3.2018.00005

2017

  • Castellana V.G., A. Tumeo, M. Minutoli, M. Lattuada, and F. Ferrandi. 2017. "Considerations on the Use of Custom Accelerators for Big Data Analytics." In Big Data Management and Processing, edited by KC Li, H Jiang and AY Zomaya. New York, New York:Chapman and Hall/CRC. PNNL-SA-121050.
  • Castellana V.G., M. Minutoli, S. Bhatt, K. Agarwal, J.T. Feo, D.G. Chavarria Miranda, and D.J. Haglin. 2017. "High-Performance Data Analytics Beyond the Relational and Graph Data Models with GEMS." In IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2017), May 29-June 2, 2017, Orlando, Florida, 1029-1038. Piscataway, New Jersey:IEEE. PNNL-SA-124655. doi:10.1109/IPDPSW.2017.70

2016

  • Chavarría-Miranda D., V.G. Castellana, A. Morari, D.J. Haglin, and J.T. Feo. 2016. "GraQL: A Query Language for High-Performance Attributed Graph Databases." In IEEE International Parallel and Distributed Processing Symposium Workshops, May 23-27, 2016, Chicago, Illinois. Piscataway, New Jersey:IEEE. PNNL-SA-116653. doi:10.1109/IPDPSW.2016.216
  • Minutoli M., V.G. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. 2016. "Efficient Synthesis of Graph Methods: a Dynamically Scheduled Architecture." In Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD 2016), November 7-10, 2016, Austin, Texas, Article No. 128. New York, New York:ACM. PNNL-SA-119594. doi:10.1145/2966986.2967030
  • Minutoli M., V.G. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. 2016. "Enabling the High Level Synthesis of Data Analytics Accelerators." In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES 2016), October 1-7, 2016, Pittsburgh, PA, Article No. 15. New York, New York:ACM. PNNL-SA-119868. doi:10.1145/2968456.2976764
  • Tumeo A., M. Ceriani, G. Palermo, M. Minutoli, V.G. Castellana, and F. Ferrandi. 2016. "Real-Time Considerations for Rugged Embedded Systems." In Rugged Embedded Systems: Computing in Harsh Environments, 1st Edition, edited by A Vega, P Bose and A Buyuktosunoglu. 39-56. Burlington, Massachusetts:Morgan Kaufmann. PNNL-SA-121051. doi:10.1016/B978-0-12-802459-1.00003-8

2015

  • Castellana V.G., A. Morari, J.R. Weaver, A. Tumeo, D.J. Haglin, O. Villa, and J. Feo. 2015. "In-Memory Graph Databases for Web-Scale Data." Computer 48, no. 3:24-35. PNNL-SA-107315. doi:10.1109/MC.2015.74
  • Minutoli M., V.G. Castellana, A. Tumeo, and F. Ferrandi. 2015. "Function Proxies for Improved Resource Sharing in High Level Synthesis." In IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, May 2-6, 2015, Vancouver, BC, Canada, 100. Los Alamitos, California:IEEE Computer Society. PNNL-SA-109324. doi:10.1109/FCCM.2015.60
  • Minutoli M., V.G. Castellana, A. Tumeo, and F. Ferrandi. 2015. "Inter-Procedural Resource Sharing in High Level Synthesis through Function Proxies." In 25th International Conference on Field-programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, UK. Piscataway, New Jersey: IEEE. PNNL-SA-111077. doi:10.1109/FPL.2015.7293958
  • Wong P.C., D.J. Haglin, D.S. Gillen, D. Chavarría-Miranda, V.G. Castellana, C.A. Joslyn, and A.R. Chappell, et al. 2015. "A Visual Analytics Paradigm Enabling Trillion-Edge Graph Exploration." In IEEE 5th Symposium on Large Data Analysis and Visualization (LDAV 2015), October 25-26, 2015, Chicago, Illinois, 57-64. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers. PNNL-SA-111289. doi:10.1109/LDAV.2015.7348072

2014

  • Castellana V.G., A. Tumeo, and F. Ferrandi. 2014. "An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems." In Design, Automation and Test in Europe Conference and Exhibition (DATE), March 24-28, 2014, Dresden, Germany, 1-4. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers. PNNL-SA-96194.
  • Morari A., V.G. Castellana, O. Villa, A. Tumeo, J.R. Weaver, D.J. Haglin, and S. Choudhury, et al. 2014. "Scaling Semantic Graph Databases in Size and Performance." IEEE Micro 34, no. 4:16-26. PNNL-SA-101644. doi:10.1109/MM.2014.39
  • Weaver J.R., V.G. Castellana, A. Morari, A. Tumeo, S. Purohit, A.R. Chappell, and D.J. Haglin, et al. 2014. "Toward a Data Scalable Solution for Facilitating Discovery of Science Resources." Parallel Computing 40, no. 10:682-696. PNNL-SA-101643. doi:10.1016/j.parco.2014.08.002

2013

  • Castellana V.G., A. Tumeo, O. Villa, D.J. Haglin, and J. Feo. 2013. "Composing Data Parallel Code for a SPARQL Graph Engine." In IEEE International Conference on Social Computing (SocialCom 2013), September 8-14, 2013, Alexandria, Virginia, 691-699. Piscataway, New Jersey:Institute of Electrical and Electronics Engineers. PNNL-SA-96193. doi:10.1109/SocialCom.2013.104
  • Morari A., V.G. Castellana, D.J. Haglin, J.T. Feo, J.R. Weaver, A. Tumeo, and O. Villa. 2013. "Accelerating semantic graph databases on commodity clusters." In IEEE International Conference on Big Data (Big Data 2013), October 6-9, 2013, Silicon Valley, California, 768-772. Piscataway, New Jersey:Institute of Electrical and Electronics Engineers. PNNL-SA-98187. doi:10.1109/BigData.2013.6691650