Computer Scientist
Computer Scientist

Biography

Joseph Manzano is a computer scientist in the High Performance Computing (HPC) group within the Advanced Computing, Mathematics, and Data Division at Pacific Northwest National Laboratory. His research focuses on performance modeling, system software technologies, and security concerns in high-performance systems. Manzano has published more than 60 peer‑reviewed publications between workshops, conferences, and journals. He is part of the organizing committee of several key workshops in top computer science conferences, such as the Machine Learning for Software Hardware Co-Design workshop series at the International Conference on Parallel Architectures and Compilation Techniques series, and an HPC-focused workshop series (Security on High Performance Computers) in the International Conference for High Performance Computing, Networking, Storage, and Analysis series, a premier venue for super computing research.

Research Interest

  • Computer Architecture
  • Cybersecurity
  • Extreme-Scale Machine Learning
  • High-Performance Computing
  • Performance Benchmarking

Education

  • PhD in electrical and computer engineering, University of Delaware
  • BS in computer science, William Paterson University of New Jersey

Publications

2023

  • Castellana V.G., N. Bohm Agostini, A.M. Limaye, V.C. Amatya, M. Minutoli, J.B. Manzano Franco, and A. Tumeo, et al. 2023. "Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis." In Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC 2023), January 16-19, 2023, Tokyo, Japan, 632-638. New York, New York:Association for Computing Machinery. PNNL-SA-179740. doi:10.1145/3566097.3568360

2022

  • Bohm Agostini N., A.M. Limaye, M. Minutoli, V.G. Castellana, J.B. Manzano Franco, A. Tumeo, and S. Curzel, et al. 2022. "SODA Synthesizer: an Open-source, Multi-level, Modular, Extensible Compiler from High-level Frameworks to Silicon." In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2022), October 30-November 3, 2022, San Diego, CA, Art. No. 18. New York, New York:Association for Computing Machinery. PNNL-SA-176485. doi:10.1145/3508352.3561101
  • Bohm Agostini N., S. Curzel, A.M. Limaye, V.C. Amatya, M. Minutoli, V.G. Castellana, and J.B. Manzano Franco, et al. 2022. "The SODA Approach: Leveraging High-Level Synthesis for Hardware/Software Co-design and Hardware Specialization: Invited." In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC 2022), July 10-14, 2022, San Francisco, CA, 1359-1362. New York, New York: Association for Computing Machinery. PNNL-SA-172445. doi:10.1145/3489517.3530628
  • Bohm Agostini N., S. Curzel, J. Zhang, A.M. Limaye, C. Tan, V.C. Amatya, and M. Minutoli, et al. 2022. "Bridging Python to Silicon: The SODA Toolchain." IEEE Micro 42, no. 5:78 - 88. PNNL-SA-169276. doi:10.1109/MM.2022.3178580
  • Bohm Agostini N., S. Curzel, V.C. Amatya, C. Tan, M. Minutoli, V.G. Castellana, and J.B. Manzano Franco, et al. 2022. "An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration." In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2022), October 30-November 3, 2022, San Diego, CA, Art. No. 6. New York, New York: Association for Computing Machinery. PNNL-SA-173501. doi:10.1145/3508352.3549424
  • Ranganath K., J.S. Firoz, J.D. Suetterlein, J.B. Manzano Franco, A. Marquez, M.V. Raugas, and D. Wong. 2022. "LC-MEMENTO: A Memory Model for Accelerated Architectures." In The 34th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2021), October 13-14, 2021. Lecture Notes in Computer Science, edited by X. Li and S. Chandrasekaran, 13181, 67-82. PNNL-SA-166245. doi:10.1007/978-3-030-99372-6_5

2021

  • Curzel S., N. Bohm Agostini, S. Song, I. Dagli, A.M. Limaye, C. Tan, and M. Minutoli, et al. 2021. "Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators." In IEEE/ACM International Conference On Computer Aided Design (ICCAD 2021), November 1-4, 2021, Munich, Germany, 1-7. Piscataway, New Jersey: IEEE. PNNL-SA-166239. doi:10.1109/ICCAD51958.2021.9643474
  • Lumsdaine A., J.S. Firoz, J.B. Manzano Franco, A. Marquez, J.D. Suetterlein, M.J. Zalewski, and T. Liu. 2021. NWGraph: A library of generic graph algorithms and data structures in C++20. PNNL-32018. Richland, WA: Pacific Northwest National Laboratory. NWGraph: A library of generic graph algorithms and data structures in C++20
  • Ranganath K., J.D. Suetterlein, J.B. Manzano Franco, S. Song, and D. Wong. 2021. "MAPA: Multi-Accelerator Pattern Allocation Policy for Multi-Tenant GPU Servers." In Proceedings of the International Conference for High Performance Computing Networking, Storage and Analysis (SC 201), November 14-19, 2021, Virtual, Online, Art. No. 99. New York, New York: Association for Computing Machinery. PNNL-SA-165192. doi:10.1145/3458817.3480853
  • Zhang J., N. Bohm Agostini, S. Song, C. Tan, A.M. Limaye, V.C. Amatya, and J.B. Manzano Franco, et al. 2021. "Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis." In IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021), July 7-9, 2021, Virtual, 218-225. Piscataway, New Jersey: IEEE. PNNL-SA-163507. doi:10.1109/ASAP52443.2021.00040

2020

  • Minutoli M., V.G. Castellana, C. Tan, J.B. Manzano Franco, V.C. Amatya, A. Tumeo, and D. Brooks, et al. 2020. "SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators." In Proceedings of the 39th International Conference On Computer-Aided Design (ICCAD 2020), November 2-5, 2020, Virtual Conference, edited by Y. Xie, Article No. 98. New York, New York: Association for Computing Machinery. PNNL-SA-155356. doi:10.1145/3400302.3415781
  • Suetterlein J.D., J.B. Manzano Franco, A. Marquez, and G.R. Gao. 2020. "On the Marriage of Asynchronous Many Task Runtimes and Big Data: A Glance." In Proceedings of the 27th International Conference on High Performance Computing, Data, and Analytics (HiPC 2020), December 16-19, 2020, Pune, India, 233-242. Piscataway, New Jersey: IEEE. PNNL-SA-157240. doi:10.1109/HiPC50609.2020.00037
  • Tumeo A., M. Minutoli, V.G. Castellana, J.B. Manzano Franco, V.C. Amatya, D. Brooks, and G. Wei. 2020. "Invited: Software defined accelerators from learning tools environment." In Invited: Software defined accelerators from learning tools environment, 1-6. Piscataway, New Jersey: IEEE. PNNL-SA-152847. doi:10.1109/DAC18072.2020.9218489

2019

  • Castellana V.G., M. Drocco, J.T. Feo, J. Firoz, T.A. Kanewala, A. Lumsdaine, and J.B. Manzano Franco, et al. 2019. "A Parallel Graph Environment for Real-World Data Analytics Workflows." In Design, Automation & Test in Europe Conference & Exhibition (DATE 2019), March 25-29, 2019, Florence, Italy, 1313-1318. Piscataway, New Jersey: IEEE. PNNL-SA-140268. doi:10.23919/DATE.2019.8715196

2018

  • Kestor G.G., B. Mutlu, J.B. Manzano Franco, O. Subasi, O. Unsal, and S. Krishnamoorthy. 2018. "Comparative Analysis of Soft-Error Detection Strategies: A Case Study with Iterative Methods." In Proceedings of the 15th ACM International Conference on Computing Frontiers (CF 2018), May 8-10, 2019, Ishia, Italy, 173-182. New York, New York: ACM. PNNL-SA-133097. doi:10.1145/3203217.3203240
  • Mutlu B., G.G. Kestor, J.B. Manzano Franco, O. Unsal, S. Chatterjee, and S. Krishnamoorthy. 2018. "Characterization of the Impact of Soft Errors on Iterative Methods." In 25TH IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, DATA, AND ANALYTICS (HiPC 2018), December 17-20, 2018, Bengaluru, Inda, 203-214. Los Alamitos, California: IEEE Computer Society. PNNL-SA-138072. doi:10.1109/HiPC.2018.00031

2017

  • Landwehr J.B., J.D. Suetterlein, J.B. Manzano Franco, A. Marquez, K.J. Barker, and G.R. Gao. 2017. "Designing Scalable Distributed Memory Models: A Case Study." In Proceedings of the Computing Frontiers Conference (CF 2017), May 15-17, 2017, Siena, Italy, 174-182. New York, New York: ACM. PNNL-SA-124960. doi:10.1145/3075564.3077425
  • Panyala A.R., D.G. Chavarria, J.B. Manzano Franco, A. Tumeo, and M. Halappanavar. 2017. "Exploring Performance and Energy Tradeoffs for Irregular Applications: A Case Study on the Tilera Many-core Architecture." Journal of Parallel and Distributed Computing 104. PNNL-SA-118976. doi:10.1016/j.jpdc.2016.06.006

2016

  • Landwehr J.B., J.D. Suetterlein, A. Marquez, J.B. Manzano Franco, and G.R. Gao. 2016. "Application Characterization at Scale: Lessons learned from developing a distributed Open Community Runtime system for High Performance Computing." In Proceedings of the ACM International Conference on Computing Frontiers (CF 2016), May 16-28, 2016, Como, Italy. New York, New York: ACM. PNNL-SA-116663. doi:10.1145/2903150.2903166
  • Suetterlein J.D., J.B. Landwehr, A. Marquez, J.B. Manzano Franco, and G.R. Gao. 2016. "Asynchronous Runtimes in Action: An Introspective Framework for a Next Gen Runtime." In IEEE International Parallel and Distributed Processing Symposium Workshops, May 23-27, 2016 Chicago, Illinois, 1744-1751. Piscataway, New Jersey: IEEE. PNNL-SA-116477. doi:10.1109/IPDPSW.2016.191
  • Suetterlein J.D., J.B. Landwehr, A. Marquez, J.B. Manzano Franco, and G.R. Gao. 2016. "Extending the Roofline Model for Asynchronous Many-Task Runtimes." In IEEE International Conference on Cluster Computing (CLUSTER 2016), Septemer 12-16, 2016, Taipei, Taiwan, 493-496. Los Alamitos, California: IEEE Computer Society. PNNL-SA-119731. doi:10.1109/CLUSTER.2016.47
  • Tallent N.R., J.B. Manzano Franco, N.A. Gawande, S. Kang, D.J. Kerbyson, A. Hoisie, and J. Cross. 2016. "Algorithm and Architecture Independent Benchmarking with SEAK." In IEEE International Parallel and Distributed Processing Symposium, May 23-27, 2016, Chicago, Illinois, 63-72. Piscataway, New Jersey: IEEE. PNNL-SA-115612. doi:10.1109/IPDPS.2016.25

2015

  • Chavarría-Miranda D., A.R. Panyala, M. Halappanavar, J.B. Manzano Franco, and A. Tumeo. 2015. "Optimizing Irregular Applications for Energy and Performance on the Tilera Many-core Architecture." In Proceedings of the 12th ACM International Conference on Computing Frontiers (CF 2015), May 18-21, 2015, Ischia, Italy, Article No. 12. New York, New York: ACM. PNNL-SA-108596. doi:10.1145/2742854.2742865
  • Chavarría-Miranda D., M. Halappanavar, S. Krishnamoorthy, J.B. Manzano Franco, A. Vishnu, and A. Hoisie. 2015. "On the Impact of Execution Models: A Case Study in Computational Chemistry." In Joint International Workshop on High-level Parallel Programming Models and Supportive Environments (HIPS) and Large-Scale Parallel Processing (LSPP), held in conjunction with the 29th IEEE International Parallel & Distributed Processing Symposium Workshop (IPDPSW 2015), May 25-29, 2015, Hyderabad, India, 255-264. Piscataway, New Jersey: IEEE. PNNL-SA-108382. doi:10.1109/IPDPSW.2015.111
  • Gawande N.A., J.B. Manzano Franco, A. Tumeo, N.R. Tallent, D.J. Kerbyson, and A. Hoisie. 2015. "Power and Performance Trade-offs for Space Time Adaptive Processing." In IEEE 20th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2015), July 27-29, 2015, Toronto, Canada, 41-48. Piscataway, New Jersey: IEEE. PNNL-SA-110779. doi:10.1109/ASAP.2015.7245703
  • Shrestha S., G.R. Gao, J.B. Manzano Franco, A. Marquez, and J.T. Feo. 2015. "Locality Aware Concurrent Start for Stencil Applications." In IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2015), February 7-11, 2015, San Francisco, California, 157-166. Piscataway, New Jersey: IEEE. PNNL-SA-108612. doi:10.1109/CGO.2015.7054196
  • Shrestha S., J.B. Manzano Franco, A. Marquez, J.T. Feo, and G.R. Gao. 2015. "Jagged Tiling for Intra-tile Parallelism and Fine-Grain Multithreading." In Languages and Compilers for Parallel Computing: 27th International Workshop (LCPC 2014), September 15-17, 2014, Hillsboro, Oregon. Lecture Notes in Computer Science, edited by J Brodman and P Tu, 8967, 161-175. New York, New York: Springer. PNNL-SA-104854. doi:10.1007/978-3-319-17473-0_11
  • Shrestha S., J.B. Manzano Franco, A. Marquez, S. Zuckerman, S. Song, and G.R. Gao. 2015. "Gregarious Data Re-structuring in a Many Core Architecture." In IEEE 17th International Conference on High Performance Computing and Communications (HPCC), 2015 IEEE 7th International Symposium on Cyberspace Safety and Security (CSS), 2015 IEEE 12th International Conference on Embedded Software and Systems (ICESS), August 24-26, 2015, New York, 712-720. Piscataway, New Jersey: IEEE. PNNL-SA-110971. doi:10.1109/HPCC-CSS-ICESS.2015.291

2014

  • Chavarría-Miranda D., J.B. Manzano Franco, S. Krishnamoorthy, A. Vishnu, K.J. Barker, and A. Hoisie. 2014. "SCaLeM: A Framework for Characterizing and Analyzing Execution Models." In Beowulf 2014: Proceedings of the 20 Years of Beowulf Workshop on Honor of Thomas Sterling's 65th Birthday, October 13-14, 2014, Annapolis, Maryland, 34-43. New York, New York: ACM. PNNL-SA-105049. doi:10.1145/2737909.2737910
  • Marquez A., J.B. Manzano Franco, S. Song, B. Meister, S. Shrestha, T. St. John, and G.R. Gao. 2014. "ACDT: Architected Composite Data Types Trading-in Unfettered Data Access for Improved Execution." In The 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2014), December 16-19, 2015, Hsinchu, Taiwan, 289-297. Piscataway, New Jersey: IEEE. PNNL-SA-105822. doi:10.1109/PADSW.2014.7097820

2012

  • Shrestha S., C. Su, A.M. White, J.B. Manzano Franco, A. Marquez, and J.T. Feo. 2012. "MODA A Framework for Memory Centric Performance Characterization." In Workshop on High-performance Infrastructure for Scalable Tools (WHIST), June 29, 2012, Venice, Italy. New York, New York: Association for Computing Machinery. PNNL-SA-91114.
  • Villa O., A. Tumeo, S. Secchi, and J.B. Manzano Franco. 2012. "Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer." IEEE Transactions on Parallel and Distributed Systems 23, no. 12:2266-2279. PNNL-SA-76835. doi:10.1109/TPDS.2012.70