Computer Scientist
Computer Scientist

Biography

Dr Antonino Tumeo received an MS degree in Informatic Engineering (2005) and a PhD in Computer Engineering (2009) from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in Pacific Northwest National Laboratory’s (PNNL) High-Performance Computing (HPC) group. He joined PNNL in 2009 as a post-doctoral research associate. Previously, he was a post-doctoral researcher at Politecnico di Milano. His research interests include modeling and simulation of high performance architectures, hardware-software codesign, electronic design automation, high-level synthesis, field-programmable gate arrays (FGPA) prototyping, and general-purpose computing on graphics processing units (GPGPU). Antonino is currently the principal investigator of SODALITE (Software Defined Accelerators from Learning Tools Environment), a project under the Real Time Machine Learning program of the Defense Advanced Research Projects Agency related to the automatic generation of machine learning accelerators, and SO(DA)2 (Software Defined Architectures for Data Analytics), a project under the Data-Model Convergence Initiative. The SO(DA)2 project is related to the development of a toolchain for efficient acceleration of emerging HPC applications (integrating scientific simulation with machine learning and data analytics) in the context of novel reconfigurable architectures.

Research Interest

  • Simulation and modeling of high performance architectures
  • Hardware-software codesign
  • FPGA prototpying
  • GPGPU computing.

Education

  • PhD in Computer Engineering, Politecnico di Milano, Italy (2009)
  • MS in Informatic Engineering, Politecnico di Milano, Italy (2005).

Affiliations and Professional Service

  • Senior Member, Institute of Electrical and Electronics Engineers
  • Senior Member, Association for Computing Machinery.

Awards and Recognitions

  • Antonino Tumeo and Oreste Villa’s research efforts lead PNNL to earn the the prestigious honor of being named a NVIDIA CUDA Research Center in 2011.

Publications

2022

  • Gawande N.A., S. Ghosh, M. Halappanavar, A. Tumeo, and A. Kalyanaraman. 2022. "Towards Scaling Community Detection on Distributed-Memory Heterogeneous Systems." Parallel Computing 111. PNNL-SA-156736. doi:10.1016/j.parco.2022.102898
  • Minutoli M., V.G. Castellana, N. Saporetti, S. Devecchi, M. Lattuada, P. Fezzardi, and A. Tumeo, et al. 2022. "Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics." IEEE Transactions on Computers 71, no. 3:520-533. PNNL-SA-144167. doi:10.1109/TC.2021.3057860

2021

  • Castellana V.G., A. Tumeo, and F. Ferrandi. 2021. "High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers." In IEEE International Parallel & Distributed Processing Symposium (IPDPS 2021), May 17-21, 2021, Virtual, Online, Paper No. 9460500. Piscataway, New Jersey:IEEE. PNNL-SA-157406. doi:10.1109/IPDPS49936.2021.00028
  • Curzel S., N. Bohm Agostini, S. Song, I. Dagli, A.M. Limaye, C. Tan, and M. Minutoli, et al. 2021. "Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators." In IEEE/ACM International Conference On Computer Aided Design (ICCAD 2021), November 1-4, 2021, Munich, Germany, 1-7. Piscataway, New Jersey: IEEE. PNNL-SA-166239. doi:10.1109/ICCAD51958.2021.9643474
  • Ferrandi F., V.G. Castellana, S. Curzel, P. Fezzardi, M. Fiorito, M. Lattuada, and M. Minutoli, et al. 2021. "Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications." In 58th ACM/IEEE Design Automation Conference (DAC 2021), December 5-9, 2021, San Francisco, CA, 1327-1330. Piscataway, New Jersey: IEEE. PNNL-SA-160619. doi:10.1109/DAC18074.2021.9586110
  • Gawande N.A., S. Ghosh, M. Halappanavar, M.H. Khan, A. Kalyanaraman, M. Minutoli, and N.R. Tallent, et al. 2021. "ExaGraph: Graph and Combinatorial Methods for Enabling Exascale Applications." International Journal of High Performance Computing Applications 35, no. 6:109434E. PNNL-SA-155863. doi:10.1177/10943420211029299
  • Tan C., C. Xie, A. Li, K.J. Barker, and A. Tumeo. 2021. "AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators." In Proceedings - Design Automation and Test In Europe , February 1-5, 2021, Virtual, Online, 2021, 1388 - 1393; Paper No. 9473955. Piscataway, New Jersey:IEEE. PNNL-SA-156552. doi:10.23919/DATE51398.2021.9473955
  • Tan C., C. Xie, T. Geng, A. Marquez, A. Tumeo, K.J. Barker, and A. Li. 2021. "ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing." IEEE Transactions on Parallel and Distributed Systems 32, no. 12:2880-2892. PNNL-SA-152862. doi:10.1109/TPDS.2021.3081074
  • Tan C., T. Geng, C. Xie, N. Bohm Agostini, J. Li, A. Li, and K.J. Barker, et al. 2021. "DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications." In IEEE 39th International Conference on Computer Design (ICCD 2021), October 24-27, 2021, Virtual, Online, 33-40. Piscataway, New Jersey:IEEE. PNNL-SA-163151. doi:10.1109/ICCD53106.2021.00018
  • Wang X., A. Tumeo, J.D. Leidel, J. Li, and Y. Chen. 2021. "HAM: Hotspot-Aware Manager for Improving Communications with 3D-Stacked Memory." IEEE Transactions on Computers 70, no. 6:833 - 848. PNNL-SA-161294. doi:10.1109/TC.2021.3066982
  • Zhang J., N. Bohm Agostini, S. Song, C. Tan, A.M. Limaye, V.C. Amatya, and J.B. Manzano Franco, et al. 2021. "Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis." In IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP 2021), July 7-9, 2021, Virtual, 218-225. Piscataway, New Jersey:IEEE. PNNL-SA-163507. doi:10.1109/ASAP52443.2021.00040

2020

  • Geng T., A. Li, R. Shi, C. Wu, T. Wang, Y. Li, and P. Haghi, et al. 2020. "AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing." In Proceedings 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO), October 17-21, 2020, Athens, Greece, 922-936. Piscataway, New Jersey:IEEE. PNNL-SA-146537. doi:10.1109/MICRO50266.2020.00079
  • Minutoli M., P. Sambaturu, M. Halappanavar, A. Tumeo, A. Kalyanaraman, and A.K. Vullinati. 2020. "PREEMPT: Scalable Epidemic Interventions Using Submodular Optimization on Multi-GPU Systems." In International Conference for High Performance Computing, Network, Storage and Analysis (SC2020), November 9-19, 2020, Atlanta, GA, 1-15. Piscataway, New Jersey:IEEE. PNNL-SA-152817. doi:10.1109/SC41405.2020.00059
  • Minutoli M., V.G. Castellana, C. Tan, J.B. Manzano Franco, V.C. Amatya, A. Tumeo, and D. Brooks, et al. 2020. "SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators." In Proceedings of the 39th International Conference On Computer-Aided Design (ICCAD 2020), November 2-5, 2020, Virtual Conference, edited by Y. Xie, Article No. 98. New York, New York:Association for Computing Machinery. PNNL-SA-155356. doi:10.1145/3400302.3415781
  • Tan C., C. Xie, A. Li, K.J. Barker, and A. Tumeo. 2020. "OpenCGRA: An Open-Source Unified Framework for Modeling,Testing, and Evaluating CGRAs." In IEEE 38th International Conference on Computer Design (ICCD 2020), October 18-21, 2020, 381-388. Piscataway, New Jersey:IEEE. PNNL-SA-152863. doi:10.1109/ICCD50377.2020.00070
  • Tumeo A., M. Minutoli, V.G. Castellana, J.B. Manzano Franco, V.C. Amatya, D. Brooks, and G. Wei. 2020. "Invited: Software defined accelerators from learning tools environment." In Invited: Software defined accelerators from learning tools environment, 1-6. Piscataway, New Jersey:IEEE. PNNL-SA-152847. doi:10.1109/DAC18072.2020.9218489

2019

  • Castellana V.G., M. Drocco, J.T. Feo, J. Firoz, T.A. Kanewala, A. Lumsdaine, and J.B. Manzano Franco, et al. 2019. "A Parallel Graph Environment for Real-World Data Analytics Workflows." In Design, Automation & Test in Europe Conference & Exhibition, March 25-29, 2019, Florence, Italy, 1313-1318. Piscataway, New Jersey:IEEE. PNNL-SA-140268. doi:10.23919/DATE.2019.8715196
  • Castellana V.G., M. Minutoli, A. Tumeo, M. Lattuada, P. Fezzardi, and F. Ferrandi. 2019. "Software Defined Architectures for Data Analytics." In Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASPDAC 2019), January 21-24, 2019, Tokyo, Japan, 711-718. New York, New York:ACM. PNNL-SA-139669. doi:10.1145/3287624.3288754
  • Friese R.D., A. Tumeo, R. Gioiosa, M.V. Raugas, and T.E. Warfel. 2019. "ADVERT: An Asynchronous Runtime for Fine-Grained Network Systems." In IEEE/ACM Third Annual Workshop on Emerging Parallel and Distributed Runtime Systems and Middleware (IPDRM 2019), November 22, 2019, Denver, CO, 9-17. Piscataway, New Jersey:IEEE. PNNL-SA-139086. doi:10.1109/IPDRM49579.2019.00006
  • Ghosh S., M. Halappanavar, A. Tumeo, A. Kalyanaraman, and A. Gebremedhin. 2019. "miniVite: A Graph Analytics Benchmarking Tool for Massively Parallel Systems." In IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS 2018), November 12, 2018, Dallas, TX, 51-56. Piscataway, New Jersey:IEEE. PNNL-SA-138790. doi:10.1109/PMBS.2018.8641631
  • Ghosh S., M. Halappanavar, A. Tumeo, and A. Kalyanaraman. 2019. "Scaling and Quality of Modularity Optimization Methods for Graph Clustering." In IEEE High Performance Extreme Computing Conference (HPEC 2019), September 24-26, 2019, Waltham, MA. Piscataway, New Jersey:IEEE. PNNL-SA-145324. doi:10.1109/HPEC.2019.8916299
  • Li J., W. Xi, A. Tumeo, B. Williams, J.D. Leidel, and Y. Chen. 2019. "PIMS: A Lightweight Processing-in-Memory Accelerator for Stencil Computations." In The International Symposium on Memory Systems (MEMSYS 2019), September 30-October 3, 2019, Washington DC, 41-52. New York, New York:ACM. PNNL-SA-146976. doi:10.1145/3357526.3357550
  • Wang X., A. Tumeo, J.D. Leidel, J. Li, and Y. Chen. 2019. "MAC: Memory Access Coalescer for 3D-Stacked Memory." In Proceedings of the 48th International Conference on Parallel Processing (ICPP 2019), August 5-8, 2019, Kyoto, Japan, Article No. 2. New York, New York:ACM. PNNL-SA-144149. doi:10.1145/3337821.3337867

2018

  • Ghosh S., M. Halappanavar, A. Tumeo, A. Kalyanaraman, and A. Gebremedhin. 2018. "Scalable Distributed Memory Community Detection Using Vite." In IEEE High Performance Extreme Computing Conference (HPEC 2018), September 25-27, 2018, Waltham, MA, 1-7. Piscataway, New Jersey:IEEE. PNNL-SA-136309. doi:10.1109/HPEC.2018.8547534
  • Ghosh S., M. Halappanavar, A. Tumeo, A. Kalyanaraman, H. Lu, D.G. Chavarría-Miranda, and M.H. Khan, et al. 2018. "Distributed Louvain Algorithm for Graph Community Detection." In IEEE International Parallel & Distributed Processing Symposium (IPDPS 2018), May 21-25, 2018, Vancouver, BC, 885-895. Los Alamitos, California:IEEE Computer Society. PNNL-SA-130211. doi:10.1109/IPDPS.2018.00098
  • Tumeo A., V.G. Castellana, and J.T. Feo. 2018. "Foreword: 8th Workshop on Irregular Applications: Architectures and Algorithms." In IEEE/ACM 8th Workshop on Irregular Applications: Architectures and Algorithms (IA3 2018), November 12, 2018, Dallas, TX, 1, vii-viii. Los Alamitos, California:IEEE Computer Society. PNNL-SA-143418. doi:10.1109/IA3.2018.00005

2017

  • Castellana V.G., A. Tumeo, M. Minutoli, M. Lattuada, and F. Ferrandi. 2017. "Considerations on the Use of Custom Accelerators for Big Data Analytics." In Big Data Management and Processing, edited by KC Li, H Jiang and AY Zomaya. New York, New York: Chapman and Hall/CRC. PNNL-SA-121050. doi:10.1201/9781315154008-14
  • Gioiosa R., A. Tumeo, J. Yin, T.E. Warfel, D.J. Haglin, and S.I. Betelu. 2017. "Exploring DataVortex Systems for Irregular Applications." In IEEE International Parallel & Distributed Processing Symposium (IPDPS 2017), May 2-June 29, 2017, Orlando, FL, 408-418. Los Alamitos, California:IEEE Computer Society. PNNL-SA-123448. doi:10.1109/IPDPS.2017.121
  • Halappanavar M., H. Lu, A. Kalyanaraman, and A. Tumeo. 2017. "Scalable Static and Dynamic Community Detection Using Grappolo." In IEEE High Performance Extreme Computing Conference (HPEC 2017), September 12-14, 2017, Waltham, Massachusetts, 1-6. Piscataway, New Jersey: IEEE. PNNL-SA-128510. doi:10.1109/HPEC.2017.8091047
  • Naim M., F. Manne, M. Halappanavar, and A. Tumeo. 2017. "Community Detection on the GPU." In IEEE International Parallel and Distributed Processing Symposium (IPDPS 2017), May 29-June 2, 2017, Orlando, Florida, 625 - 634. Piscataway, New Jersey: IEEE. PNNL-SA-123598. doi:10.1109/IPDPS.2017.16
  • Panyala A.R., D.G. Chavarria, J.B. Manzano Franco, A. Tumeo, and M. Halappanavar. 2017. "Exploring Performance and Energy Tradeoffs for Irregular Applications: A Case Study on the Tilera Many-core Architecture." Journal of Parallel and Distributed Computing 104. PNNL-SA-118976. doi:10.1016/j.jpdc.2016.06.006
  • Tumeo A. 2017. "Architecture Independent Integrated Early Performance and Energy Estimation." In Eighth International Green and Sustainable Computing Conference (IGSC 2017), October 23-25, 2017, Orlando, FL, 1-6. Piscataway, New Jersey: IEEE. PNNL-SA-129380. doi:10.1109/IGCC.2017.8323602

2016

  • Minutoli M., V.G. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. 2016. "Efficient Synthesis of Graph Methods: a Dynamically Scheduled Architecture." In Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD 2016), November 7-10, 2016, Austin, Texas, Article No. 128. New York, New York: ACM. PNNL-SA-119594. doi:10.1145/2966986.2967030
  • Minutoli M., V.G. Castellana, A. Tumeo, M. Lattuada, and F. Ferrandi. 2016. "Enabling the High Level Synthesis of Data Analytics Accelerators." In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES 2016), October 1-7, 2016, Pittsburgh, PA, Article No. 15. New York, New York: ACM. PNNL-SA-119868. doi:10.1145/2968456.2976764
  • Tallent N.R., K.J. Barker, R. Gioiosa, A. Marquez, G. Kestor, S. Song, and A. Tumeo, et al. 2016. "Assessing Advanced Technology in CENATE." In Proceedings of the IEEE International Conference on Networking, Architecture, and Storage (NAS 2016), August 8-10, 2016, Long Beach, California. Piscataway, New Jersey: IEEE. PNNL-SA-119257. doi:10.1109/NAS.2016.7549392
  • Tumeo A., M. Ceriani, G. Palermo, M. Minutoli, V.G. Castellana, and F. Ferrandi. 2016. "Real-Time Considerations for Rugged Embedded Systems." In Rugged Embedded Systems: Computing in Harsh Environments, 1st Edition, edited by A Vega, P Bose and A Buyuktosunoglu. 39-56. Burlington, Massachusetts: Morgan Kaufmann. PNNL-SA-121051. doi:10.1016/B978-0-12-802459-1.00003-8

2015

  • Castellana V.G., A. Morari, J.R. Weaver, A. Tumeo, D.J. Haglin, O. Villa, and J. Feo. 2015. "In-Memory Graph Databases for Web-Scale Data." Computer 48, no. 3:24-35. PNNL-SA-107315. doi:10.1109/MC.2015.74
  • Chavarría-Miranda D., A.R. Panyala, M. Halappanavar, J.B. Manzano Franco, and A. Tumeo. 2015. "Optimizing Irregular Applications for Energy and Performance on the Tilera Many-core Architecture." In Proceedings of the 12th ACM International Conference on Computing Frontiers (CF 2015), May 18-21, 2015, Ischia, Italy, Article No. 12. New York, New York: ACM. PNNL-SA-108596. doi:10.1145/2742854.2742865
  • Gawande N.A., J.B. Manzano Franco, A. Tumeo, N.R. Tallent, D.J. Kerbyson, and A. Hoisie. 2015. "Power and Performance Trade-offs for Space Time Adaptive Processing." In IEEE 20th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2015), July 27-29, 2015, Toronto, Canada, 41-48. Piscataway, New Jersey: IEEE. PNNL-SA-110779. doi:10.1109/ASAP.2015.7245703
  • Minutoli M., V.G. Castellana, A. Tumeo, and F. Ferrandi. 2015. "Function Proxies for Improved Resource Sharing in High Level Synthesis." In IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, May 2-6, 2015, Vancouver, BC, Canada, 100. Los Alamitos, California: IEEE Computer Society. PNNL-SA-109324. doi:10.1109/FCCM.2015.60
  • Minutoli M., V.G. Castellana, A. Tumeo, and F. Ferrandi. 2015. "Inter-Procedural Resource Sharing in High Level Synthesis through Function Proxies." In 25th International Conference on Field-programmable Logic and Applications (FPL 2015), September 2-4, 2015, London, UK. Piscataway, New Jersey: IEEE. PNNL-SA-111077. doi:10.1109/FPL.2015.7293958
  • Naim M., F. Manne, M. Halappanavar, A. Tumeo, and J. Langguth. 2015. "Optimizing Approximate Weighted Matching on Nvidia Kepler K40." In IEEE 22nd International Conference on High Performance Computing (HiPC 2015), December 16-19, 2015, Bangalore, India, 105-114. Los Alamitos, California: IEEE Computer Society. PNNL-SA-113350. doi:10.1109/HiPC.2015.15

2014

  • Castellana V.G., A. Tumeo, and F. Ferrandi. 2014. "An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems." In Design, Automation and Test in Europe Conference and Exhibition, March 24-28, 2014, Dresden, Germany, 1-4. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers. PNNL-SA-96194. doi: 10.7873/DATE.2014.192
  • Morari A., A. Tumeo, D. Chavarría-Miranda, O. Villa, and M. Valero. 2014. "Scaling Irregular Applications through Data Aggregation and Software Multithreading." In IEEE 28th International Parallel and Distributed Processing Symposium, May 19-23, 2014, Phoenix, Arizona, 1126-1135. Piscataway, New Jersey: IEEE. PNNL-SA-96137. doi:10.1109/IPDPS.2014.117
  • Morari A., V.G. Castellana, O. Villa, A. Tumeo, J.R. Weaver, D.J. Haglin, and S. Choudhury, et al. 2014. "Scaling Semantic Graph Databases in Size and Performance." IEEE Micro 34, no. 4:16-26. PNNL-SA-101644. doi:10.1109/MM.2014.39
  • Tumeo A., N.A. Gawande, and O. Villa. 2014. "A Flexible CUDA LU-based Solver for Small, Batched Linear Systems." In Numerical Computations with GPUs, edited by V Kindratenko. 87-101. Cham: Springer International Publishing. PNNL-SA-100792. doi: 10.1007/978-3-319-06548-9_5
  • Weaver J.R., V.G. Castellana, A. Morari, A. Tumeo, S. Purohit, A.R. Chappell, and D.J. Haglin, et al. 2014. "Toward a Data Scalable Solution for Facilitating Discovery of Science Resources." Parallel Computing 40, no. 10:682-696. PNNL-SA-101643. doi:10.1016/j.parco.2014.08.002

2013

  • Castellana V.G., A. Tumeo, O. Villa, D.J. Haglin, and J. Feo. 2013. "Composing Data Parallel Code for a SPARQL Graph Engine." In IEEE International Conference on Social Computing (SocialCom 2013), September 8-14, 2013, Alexandria, Virginia, 691-699. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers. PNNL-SA-96193. doi:10.1109/SocialCom.2013.104
  • Ceriani M., G. Palermo, S. Secchi, A. Tumeo, and O. Villa. 2013. "Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping." In IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), April 28-30, 2013, Seattle, Washington, 238. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers. PNNL-SA-90226. doi:10.1109/FCCM.2013.62
  • Chappell A.R., S. Choudhury, J.T. Feo, D.J. Haglin, A. Morari, S. Purohit, and K.L. Schuchardt, et al. 2013. "Toward a Data Scalable Solution for Facilitating Discovery of Scientific Data Resources." In DISCS-2013: Proceedings of the International Workshop on Data-Intensive Scalable Computing Systems, November 18, 2013, Denver, CO, 55-60. New York, New York:Association for Computing Machinery. PNNL-SA-98169. doi:10.1145/2534645.2534655
  • Ferrandi F., P. Lanzi, C. Pilato, D. Sciuto, and A. Tumeo. 2013. "Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems." In NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), June 24-27, 2013, Torino, Italy, 47-54. Torino:Institute of Electrical and Electronics Engineers. PNNL-SA-95042. doi:10.1109/AHS.2013.6604225
  • Lovergine S., A. Tumeo, O. Villa, and F. Ferrandi. 2013. "YAPPA: a Compiler-Based Parallelization Framework for Irregular Applications on MPSoCs." In IEEE International Symposium on Rapid System Prototyping (RSP 2013), October 3-4, 2013, Montreal, Quebec, Canada, 123-129. Montreal:Institute of Electrical and Electronics Engineers. PNNL-SA-96169. doi:10.1109/RSP.2013.6683968
  • Morari A., V.G. Castellana, D.J. Haglin, J.T. Feo, J.R. Weaver, A. Tumeo, and O. Villa. 2013. "Accelerating semantic graph databases on commodity clusters." In IEEE International Conference on Big Data (Big Data 2013), October 6-9, 2013, Silicon Valley, California, 768-772. Piscataway, New Jersey:Institute of Electrical and Electronics Engineers. PNNL-SA-98187. doi:10.1109/BigData.2013.6691650
  • Secchi S., M. Ceriani, A. Tumeo, O. Villa, G. Palermo, and L. Raffo. 2013. "Exploring Hardware Support For Scaling Irregular Applications on Multi-node Multi-core Architectures." In IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2013), June 5--7, 2013, Washington DC, 309-313. Piscataway, New Jersey:Institute of Electrical and Electronics Engineers. PNNL-SA-95041. doi:10.1109/ASAP.2013.6567595
  • Tumeo A., O. Villa, S. Secchi, and D. Chavarría-Miranda. 2013. "Efficient Aho-Corasick String Matching on Emerging Multicore Architectures." In Multicore Computing: Algorithms, Architectures, and Applications, edited by S Rajasekaran, et al. 143-170. Boca Raton, Florida: Chapman and Hall/CRC Press. PNNL-SA-84463. doi: 10.1201/b16293-12
  • Villa O., M. Fatica, N.A. Gawande, and A. Tumeo. 2013. "Power/Performance Trade-offs of Small Batched LU Based Solvers on GPUs." In Euro-Par 2013 Parallel Processing. 19th International Conference, August 26-30, 2013, Aachen, Germany. Lecture Notes in Computer Science, edited by F Wolf, B Mohr and D an Mey, 8097, 813-825. Berlin:Springer-Verlag. PNNL-SA-93959. doi:10.1007/978-3-642-40047-6_81
  • Villa O., N.A. Gawande, and A. Tumeo. 2013. "Accelerating Subsurface Transport Simulation on Heterogeneous Clusters." In IEEE International Conference on Cluster Computing (CLUSTER 2013), September 23-27, 2013, Indianapolis, Indiana, 1-8. Piscataway, New Jersey:Institute of Electrical and Electronics Engineers. PNNL-SA-96124. doi:10.1109/CLUSTER.2013.6702656

2012

  • Feo J.T., O. Villa, A. Tumeo, and S. Secchi. 2012. "Irregular Applications: Architectures & Algorithms." In IAAA 2011 - Proceedings of the First Workshop on Irregular Applications: Architectures & Algorithms, November 12-18, 2011, Seattle, Washington. New York, New York:Association for Computing Machinery. PNNL-SA-84461. doi:10.1145/2089142.2089144
  • Halappanavar M., J.T. Feo, O. Villa, A. Tumeo, and A. Pothen. 2012. "Approximate Weighted Matching On Emerging Manycore and Multithreaded Architectures." International Journal of High Performance Computing Applications 26, no. 4:413-430. PNNL-SA-78710. doi:10.1177/1094342012452893
  • Morari A., A. Tumeo, O. Villa, S. Secchi, and M. Valero. 2012. "Efficient Sorting on the Tilera Manycore Architecture." In IEEE 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2012), October 24-26, 2012, New York, 171-178. Piscataway, New Jersey:Institute of Electrical and Electronics Engineers. PNNL-SA-90686. doi:10.1109/SBAC-PAD.2012.41
  • Secchi S., A. Tumeo, and O. Villa. 2012. "A Bandwidth-Optimized Multi-Core Architecture for Irregular Applications." In 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2012), May 13-16, 2012, Ottawa, Ontario, Canada, 580-587. Los Alamitos, California:IEEE Computer Society. PNNL-SA-79924. doi:10.1109/CCGrid.2012.53
  • Tumeo A., O. Villa, and D. Chavarra-Miranda. 2012. "Aho-Corasick String Matching on Shared and Distributed Memory Parallel Architectures." IEEE Transactions on Parallel and Distributed Systems 23, no. 3:436-443. PNNL-SA-74248. doi:10.1109/TPDS.2011.181
  • Tumeo A., O. Villa, and D. Chavarría-Miranda. 2012. "Hardware Architectures for Data-Intensive Computing Problems: A Case Study for String Matching." In Data-Intensive Computing: Advances, Applications & Architectures, edited by I Gorton and DK Gracio. 24-47. New York, New York: Cambridge University Press. PNNL-SA-86496. doi:10.1017/CBO9780511844409.003
  • Tumeo A., S. Secchi, and O. Villa. 2012. "Designing Next Generation Massively Multithreaded Architectures for Irregular Applications." Computer 45, no. 8:53-61. PNNL-SA-86495. doi: 10.1109/MC.2012.193
  • Villa O., A. Tumeo, S. Ciraci, J.A. Daily, and J.C. Fuller. 2012. "A High Performance Computing Network and System Simulator for the Power Grid: NGNS^2." In 2012 SC Companion: High Performance Computing, Networking and Analytics for the Power Grid (SCC), November 10-16, 2012, Salt Lake City, Utah, 313-322. Los Alamitos, California:IEEE Computer Society Press. PNNL-SA-90518. doi:10.1109/SC.Companion.2012.50
  • Villa O., A. Tumeo, S. Secchi, and J.B. Manzano Franco. 2012. "Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer." IEEE Transactions on Parallel and Distributed Systems 23, no. 12:2266-2279. PNNL-SA-76835. doi:10.1109/TPDS.2012.70

2011

  • Feo J.T., O. Villa, A. Tumeo, and S. Secchi. 2011. "Towards Efficient Execution of Irregular Applications: Panel Outline." In IAAA 2011: Proceedings of the First Workshop on Irregular Applications: Architectures & Algorithms, November 12-18, 2011, Seattle, Washington, 43-44. New York, New York:Association of Computing Machinery. PNNL-SA-84462. doi:10.1145/2089142.2089154
  • Secchi S., A. Tumeo, and O. Villa. 2011. "Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT." In 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2011), May 23-26, 2011, Newport Beach, California, 275-284. Los Alamitos, California:IEEE Computer Society. PNNL-SA-76834. doi:10.1109/CCGrid.2011.39
  • Tumeo A., S. Secchi, and O. Villa. 2011. "Experiences with string matching on the Fermi Architecture." In Architecture of Computing Systems - ARCS 2011: 24th International Conference, February 24-25, 2011, Como, Italy. Lecture Notes in Computer Science, edited by M Berekovic, et al, 6566, 26-37. Berlin:Springer-Verlag. PNNL-SA-75647. doi:10.1007/978-3-642-19137-4_3

2010

  • Siegel J., O. Villa, S. Krishnamoorthy, A. Tumeo, and X. Li. 2010. "Efficient Sparse Matrix-Matrix Multiplication on Heterogeneous High Performance Systems." In Proceedings of the IEEE International Conference on Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS 2010), 1-8. Piscataway, New Jersey: Institute of Electrical and Electronic Engineers. PNNL-SA-74056. doi:10.1109/CLUSTERWKSP.2010.5613109
  • Tumeo A., and O. Villa. 2010. "Accelerating DNA analysis applications on GPU clusters." In 8th IEEE Symposium on Application Specific Processors (SASP), June 13-14, 2010, Anaheim, California, 71-76. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers. PNNL-SA-72803. doi:10.1109/SASP.2010.5521145
  • Villa O., A. Tumeo, and D. Sciuto. 2010. "Efficient pattern matching on GPUs for intrusion detection systems." In Proceedings of the 7th ACM International Conference on Computing Frontiers, 87-88. New York, New York: Association for Computing Machinery. PNNL-SA-70334. doi:10.1145/1787275.1787296