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Staff information

Mahantesh Halappanavar

Mahantesh Halappanavar

High Performance Computing
Pacific Northwest National Laboratory
PO Box 999
MSIN: J4-30
Richland, WA 99352


Dr. Mahantesh Halappanavar joined Pacific Northwest National Laboratory in December 2009. His work focuses on parallel graph algorithms and spans several applications including contingency analysis of electric power grids, statistical textual analysis, numerical linear algebra, information security and fault tolerance. He explores the interplay of algorithm design, architectural features, and input characteristics targeting massively multithreaded architectures such as the Cray XMT and emerging multicore (Intel, AMD) and manycore (nVIDIA) platforms.

Mahantesh graduated in 2009 with a Ph.D. in Computer Science from the Old Dominion University, Norfolk, Virginia. His doctoral research was in the emerging interdisciplinary field known as combinatorial scientific computing (CSC) that employs combinatorial algorithmic techniques to solve scientific computing problems. He developed new approximation algorithms for graph matching – a fundamental combinatorial problem with numerous applications in science and engineering. He also developed software targeting the Department of Energy's leadership class machines for the approximate graph matching problem and demonstrated scalability across tens of thousands of processors.

Research Interests

  • Graph Algorithms
  • Parallel Computing
  • Combinatorial Scientific Computing
  • Electric Power Grids
  • Statistical Textual Analysis

Education and Credentials

  • Ph.D., Old Dominion University
  • M.S., Old Dominion University
  • B.E., Karnataka University, India

Affiliations and Professional Service

  • Member of the Society of Industrial and Applied Mathematics (SIAM)
  • Member of the Association for Computing Machinery (ACM)

Awards and Recognitions

  • Recipient of Old Dominion University Graduate Fellowship for year 2005-2006 with the distinction of being best-of-the-best doctoral students
  • Recipient of Dean’s Education Abroad Award in June 2005
  • Second rank in the University for Bachelors degree (B.E.)

PNNL Publications


  • Hogan EA, JE Cotilla Sanchez, M Halappanavar, S Wang, PS Mackey, P Hines, and Z Huang. 2013. "Towards Effective Clustering Techniques for the Analysis of Electric Power Grids." In HiPCNA-PG: Proceedings of the 3rd International Workshop on High Performance Computing, Networking and Analytics for the Power Grid, November 17-21, 2013, Denver Colorado, p. Article No. 1.  ACM , New York, NY.  doi:10.1145/2536780.2536785
  • Hogan EA, PSY Hui, S Choudhury, M Halappanavar, KJ Oler, and CA Joslyn. 2013. "Towards a Multiscale Approach to Cybersecurity Modeling." In IEEE International Conference on Technologies for Homeland Security (HST 2013), November 12-14, 2013, Waltham, MA, pp. 80-85.  IEEE, Piscataway, NJ.  doi:10.1109/THS.2013.6698980
  • Ali N, S Krishnamoorthy, M Halappanavar, and JA Daily. 2013. "Multi-fault Tolerance for Cartesian Data Distributions." International Journal of Parallel Programming 41(3):469-493.  doi:10.1007/s10766-012-0218-5
  • Halappanavar M, S Choudhury, EA Hogan, PSY Hui, JR Johnson, III, I Ray, and LB Holder. 2013. "Towards A Network-of-Networks Framework for Cyber Security." In IEEE Intelligence and Security Informatics, June 4-7, 2013, Seattle, Washington, pp. 106-108.  Institute of Electrical and Electronics Engineers, Piscataway, NJ.  doi:10.1109/ISI.2013.6578796
  • Ramuhalli P, M Halappanavar, JB Coble, and M Dixit. 2013. "Towards A Theory of Autonomous Reconstitution of Compromised Cyber-Systems." In IEEE International Conference on Technologies for Homeland Security (HST 2013), November 12-14, 2013, Waltham, MA, pp. 577-583.  Institute of Electrical and Electronics Engineers Inc., Piscataway, NJ.  doi:10.1109/THS.2013.6699067


  • Azad MA, M Halappanavar, S Rajamanickam, EG Boman, A Khan, and A Pothen. 2012. "Multithreaded Algorithms for Maximum Matching in Bipartite Graphs." In IEEE 26th International Parallel & Distributed Processing Symposium (IPDPS 2012), May 12-25, 2012, Shanghai, China, pp. 860-872.  IEEE Computer Society, Los Alamitos, CA.  doi:10.1109/IPDPS.2012.82
  • Scherrer C, A Tewari, M Halappanavar, and DJ Haglin. 2012. "Feature Clustering for Accelerating Parallel Coordinate Descent." In Advances in Neural Information Processing Systems 25: 26th Annual Conference on Neural Information Processing Systems (NIPS 2012), December 3-6, 2012, Lake Tahoe, Nevada, ed. P. Bartlett, et al, pp. 28-36.  Neural Information Processing Systems Foundation, La Jolla, CA. 
  • Scherrer C, M Halappanavar, A Tewari, and DJ Haglin. 2012. "Scaling Up Coordinate Descent Algorithms for Large l1 Regularization Problems." In Proceedings of the 29th International Conference on Machine Learning (ICML 2012), June 26, 2012, Edinburgh, Scotland, ed. J Langford adn J Pineau.  International Machine Learning Society, Madison, WI. 
  • Catalyurek UV, JT Feo, AH Gebremedhin, M Halappanavar, and A Pothen. 2012. "Multithreaded Algorithms for Graph Coloring." Parallel Computing 38(10-11):576-594.  doi:10.1016/j.parco.2012.07.001
  • Halappanavar M, JT Feo, K Dempsey, H Ali, and S Bhowmick. 2012. "A Novel Multithreaded Algorithm For Extracting Maximal Chordal Subgraphs." In 41st International Conference on Parallel Processing (ICPP), September 10-13, 2012, Pittsburgh, Pennsylvania, pp. 58-67.  Institute of Electrical and Electronics Engineers, Piscataway, NJ.  doi:10.1109/ICPP.2012.10
  • Halappanavar M, JT Feo, O Villa, A Tumeo, and A Pothen. 2012. "Approximate Weighted Matching On Emerging Manycore and Multithreaded Architectures." International Journal of High Performance Computing Applications 26 (4 ):413-430.  doi:10.1177/1094342012452893
  • Halappanavar M, Y Chen, RD Adolf, DJ Haglin, Z Huang, and MJ Rice. 2012. "Towards Efficient N - x Contingency Selection Using Group Betweenness Centrality." In SC Companion: High Performance Computing, Networking, Storage and Analysis (SCC 2012), November 10-16, 2012, Salt Lake City, UT, pp. 273 - 282.  Institute of Electrical and Electronics Engineers, Piscataway, NJ.  doi:10.1109/SC.Companion.2012.45
  • Khan A, DF Gleich, A Pothen, and M Halappanavar. 2012. "A Multithreaded Algorithm for Network Alignment Via Approximate Matching." In International Conference for High Performance Computing, Networking, Storage and Analysis (SC), November 10-16, 2012, Salt Lake City, Utah.  Institute of Electrical and Electronics Engineers, Piscataway, NJ.  doi:10.1109/SC.2012.8


  • Adolf RD, DJ Haglin, M Halappanavar, Y Chen, and Z Huang. 2011. "Techniques for Improving Filters in Power Grid Contingency Analysis." In Proceedings of the 7th International Conference on Machine Learning and Data Mining in Pattern Recognition (MLDM), August 30-September 3, 2011, New York. Lecture Notes in Computer Science, vol. 6871, ed. P Perner, pp. 599-611.  Springer-Verlag, Berlin, Germany.  doi:10.1007/978-3-642-23199-5_44
  • Ali N, S Krishnamoorthy, M Halappanavar, and JA Daily. 2011. "Tolerating Correlated Failures for Generalized Cartesian Distributions via Bipartite Matching." In Proceedings of the 8th ACM International Conference on Computing Frontiers (CF 2011), May 3-5, 2011, Ischia, Italy.  Association for Computing Machinery, New York, NY.  doi:10.1145/2016604.2016649
  • Catalyurek U, F Dobrian, AH Gebremedhin, M Halappanavar, and A Pothen. 2011. "Distributed-memory Parallel Algorithms for Matching and Coloring." In IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW 2011), May 16-20, 2011 Anchorage, Alaska, pp. 1971-1980.  Institute of Electrical and Electronics Engineers, Piscataway, NJ.  doi:10.1109/IPDPS.2011.360

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