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Antonino Tumeo

Antonino Tumeo

High Performance Computing
Scientist
Pacific Northwest National Laboratory
PO Box 999
MSIN: J4-30
Richland, WA 99352
509/371-6820

Biography

Dr. Antonino Tumeo received the M.S degree in Informatic Engineering, in 2005, and the Ph.D degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in the PNNL's High Peformance Computing group. He Joined PNNL in 2009 as a post doctoral research associate. Previously, he was a post doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing.

Research Interests

  • Simulation and modeling of high performance architectures
  • Hardware-software codesign
  • FPGA prototpying
  • GPGPU computing

Education and Credentials

  • 2009 PhD in Computer Engineering - Politecnico di Milano (Italy)
  • 2005 MSc in Information Engineering - Politecnico di Milano (Italy)

Affiliations and Professional Service

  • IEEE Member
  • ACM Member

Awards and Recognitions

  • 2011 CUDA Research Center

PNNL Publications

2014

  • Morari A, A Tumeo, D Chavarría-Miranda, O Villa, and M Valero. 2014. "Scaling Irregular Applications through Data Aggregation and Software Multithreading." In IEEE 28th International Parallel and Distributed Processing Symposium, May 19-23, 2014, Phoenix, Arizona, pp. 1126-1135.  IEEE, Piscataway, NJ.  doi:10.1109/IPDPS.2014.117
  • Castellana VG, A Tumeo, and F Ferrandi. 2014. "An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems." In Design, Automation and Test in Europe Conference and Exhibition (DATE), March 24-28, 2014, Dresden, Germany, pp. 1-4.  Institute of Electrical and Electronics Engineers, Piscataway, NJ. 

2013

  • Morari A, VG Castellana, DJ Haglin, JT Feo, JR Weaver, A Tumeo, and O Villa. 2013. "Accelerating semantic graph databases on commodity clusters." In IEEE International Conference on Big Data (Big Data 2013), October 6-9, 2013, Silicon Valley, California, pp. 768-772.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/BigData.2013.6691650
  • Secchi S, M Ceriani, A Tumeo, O Villa, G Palermo, and L Raffo. 2013. "Exploring Hardware Support For Scaling Irregular Applications on Multi-node Multi-core Architectures." In IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2013), June 5--7, 2013, Washington DC, pp. 309-313.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/ASAP.2013.6567595
  • Castellana VG, A Tumeo, O Villa, DJ Haglin, and J Feo. 2013. "Composing Data Parallel Code for a SPARQL Graph Engine." In IEEE International Conference on Social Computing (SocialCom 2013), September 8-14, 2013, Alexandria, Virginia, pp. 691-699.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/SocialCom.2013.104
  • Ceriani M, G Palermo, S Secchi, A Tumeo, and O Villa. 2013. "Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping." In IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), April 28-30, 2013, Seattle, Washington, p. 238.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/FCCM.2013.62
  • Chappell AR, S Choudhury, JT Feo, DJ Haglin, A Morari, S Purohit, KL Schuchardt, A Tumeo, JR Weaver, and O Villa. 2013. "Toward a Data Scalable Solution for Facilitating Discovery of Scientific Data Resources." In DISCS-2013: Proceedings of the International Workshop on Data-Intensive Scalable Computing Systems, November 18, 2013, Denver, CO, pp. 55-60.  Association for Computing Machinery , New York, NY.  doi:10.1145/2534645.2534655
  • Ferrandi F, PL Lanzi, C Pilato, D Sciuto, and A Tumeo. 2013. "Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems." In NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), June 24-27, 2013, Torino, Italy, pp. 47-54.  Institute of Electrical and Electronics Engineers , Torino, Italy.  doi:10.1109/AHS.2013.6604225
  • Lovergine S, A Tumeo, O Villa, and F Ferrandi. 2013. "YAPPA: a Compiler-Based Parallelization Framework for Irregular Applications on MPSoCs." In IEEE International Symposium on Rapid System Prototyping (RSP 2013), October 3-4, 2013, Montreal, Quebec, Canada, pp. 123-129.  Institute of Electrical and Electronics Engineers , Montreal, Canada.  doi:10.1109/RSP.2013.6683968
  • Villa O, M Fatica, NA Gawande, and A Tumeo. 2013. "Power/Performance Trade-offs of Small Batched LU Based Solvers on GPUs." In Euro-Par 2013 Parallel Processing. 19th International Conference, August 26-30, 2013, Aachen, Germany. Lecture Notes in Computer Science, vol. 8097, ed. F Wolf, B Mohr and D an Mey, pp. 813-825.  Springer-Verlag, Berlin, Germany.  doi:10.1007/978-3-642-40047-6_81
  • Villa O, NA Gawande, and A Tumeo. 2013. "Accelerating Subsurface Transport Simulation on Heterogeneous Clusters." In IEEE International Conference on Cluster Computing (CLUSTER 2013), September 23-27, 2013, Indianapolis, Indiana, pp. 1-8.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/CLUSTER.2013.6702656

2012

  • Secchi S, A Tumeo, and O Villa. 2012. "A Bandwidth-Optimized Multi-Core Architecture for Irregular Applications." In 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2012), May 13-16, 2012, Ottawa, Ontario, Canada, pp. 580-587.  IEEE Computer Society, Los Alamitos, CA.  doi:10.1109/CCGrid.2012.53
  • Feo JT, O Villa, A Tumeo, and S Secchi. 2012. "Irregular Applications: Architectures & Algorithms." In IAAA 2011 - Proceedings of the First Workshop on Irregular Applications: Architectures & Algorithms, November 12-18, 2011, Seattle, Washington.  Association for Computing Machinery, New York, NY.  doi:10.1145/2089142.2089144
  • Halappanavar M, JT Feo, O Villa, A Tumeo, and A Pothen. 2012. "Approximate Weighted Matching On Emerging Manycore and Multithreaded Architectures." International Journal of High Performance Computing Applications 26 (4 ):413-430.  doi:10.1177/1094342012452893
  • Morari A, A Tumeo, O Villa, S Secchi, and M Valero. 2012. "Efficient Sorting on the Tilera Manycore Architecture." In IEEE 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2012), October 24-26, 2012, New York, pp. 171-178.  Institute of Electrical and Electronics Engineers , Piscataway, NJ.  doi:10.1109/SBAC-PAD.2012.41
  • Tumeo A, S Secchi, and O Villa. 2012. "Designing Next Generation Massively Multithreaded Architectures for Irregular Applications." Computer 45(8):53-61. 
  • Tumeo A, O Villa, and D Chavarría-Miranda. 2012. "Aho-Corasick String Matching on Shared and Distributed Memory Parallel Architectures." IEEE Transactions on Parallel and Distributed Systems 23(3):436-443.  doi:10.1109/TPDS.2011.181
  • Tumeo A, O Villa, and D Chavarría-Miranda. 2012. "Hardware Architectures for Data-Intensive Computing Problems: A Case Study for String Matching." Chapter 3 in Data-Intensive Computing: Advances, Applications & Architectures, ed. I Gorton and DK Gracio, pp. 24-47.  Cambridge University Press, New York, NY. 
  • Villa O, A Tumeo, S Ciraci, JA Daily, and JC Fuller. 2012. "A High Performance Computing Network and System Simulator for the Power Grid: NGNS^2." In 2012 SC Companion: High Performance Computing, Networking and Analytics for the Power Grid (SCC), November 10-16, 2012, Salt Lake City, Utah, pp. 313-322.  IEEE Computer Society Press, Los Alamitos, CA.  doi:10.1109/SC.Companion.2012.50
  • Villa O, A Tumeo, S Secchi, and JB Manzano Franco. 2012. "Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer." IEEE Transactions on Parallel and Distributed Systems 23(12):2266-2279.  doi:10.1109/TPDS.2012.70

2011

  • Secchi S, A Tumeo, and O Villa. 2011. "Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT." In 11th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2011), May 23-26, 2011, Newport Beach, California, pp. 275-284.  IEEE Computer Society, Los Alamitos, CA.  doi:10.1109/CCGrid.2011.39
  • Feo JT, O Villa, A Tumeo, and S Secchi. 2011. "Towards Efficient Execution of Irregular Applications: Panel Outline." In IAAA 2011: Proceedings of the First Workshop on Irregular Applications: Architectures & Algorithms, November 12-18, 2011, Seattle, Washington, pp. 43-44.  Association of Computing Machinery, New York, NY.  doi:10.1145/2089142.2089154
  • Tumeo A, S Secchi, and O Villa. 2011. "Experiences with string matching on the Fermi Architecture." In Architecture of Computing Systems - ARCS 2011: 24th International Conference, February 24-25, 2011, Como, Italy. Lecture Notes in Computer Science, vol. 6566, ed. M Berekovic, et al, pp. 26-37.  Springer-Verlag, Berlin, Germany.  doi:10.1007/978-3-642-19137-4_3

2010

  • Tumeo A, and O Villa. 2010. "Accelerating DNA analysis applications on GPU clusters." In 8th IEEE Symposium on Application Specific Processors (SASP), June 13-14, 2010, Anaheim, California, pp. 71-76.  Institute of Electrical and Electronics Engineers, Piscataway, NJ.  doi:10.1109/SASP.2010.5521145
  • Siegel J, O Villa, S Krishnamoorthy, A Tumeo, and X Li. 2010. "Efficient Sparse Matrix-Matrix Multiplication on Heterogeneous High Performance Systems." In Proceedings of the IEEE International Conference on Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS 2010), pp. 1-8.  Institute of Electrical and Electronic Engineers, Piscataway, NJ.  doi:10.1109/CLUSTERWKSP.2010.5613109
  • Villa O, A Tumeo, and D Sciuto. 2010. "Efficient pattern matching on GPUs for intrusion detection systems." In Proceedings of the 7th ACM International Conference on Computing Frontiers, pp. 87-88.  Association for Computing Machinery, New York, NY.  doi:10.1145/1787275.1787296

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